TM 55-4920-401-13&P
7 . Q u a d r u p l e 2 - I n p u t N A N D G a t e
and the operation of a single gate is summarized in
(SN5400). Gate pins are identified in figure 1-33
Table 1-6.
Table 1-6. Truth Table of 2- Input NAND Gate
Figure 1-33. Quadruple 2-Input NAND Gate.
8 . Q u a d 2 - I n p u t N O R G a t e
level. If both inputs are at the 0 level, the output is
(SN5402). If one or both inputs of a single gate
at the 1 level. Input and output relationships are
(fig. 1-34) are at the 1 level, the output is at the 0
summarized in Table 1-7.
Figure 1-34. Quad 2-Input NOR Gate.
1-35
