(4) Probe Controller. The probe controller
portion of the tester contains circuitry that con-
tyrols the heating of various types of temperature
probes. The temperature to which a probe is to be
heated is set using the PROBE CONTROL while ob-
serving the setting on the TEMP ºC indicator. Pre-
cision thermocouples in the temperature probes ac-
curately measure the probe temperature which is
displayed by the TEMP ºC indicator. Both the set
temperature signal and the measured temperature
signal are appplied to a voltage comparator in the
probe control circuit. This circuit drives the gates of
SCR's 1 and 2 and controls the application of full-
wave power from transformer T1 to the heater
probes. The PROBE POWER lamp burns con-
tinously when continuous power is applied to the
probes. It extinguishes when power is removed from
the probes and flahses when their temperature is
(5) Insulation Check Circuit. This circuit
measures the insulation resistance between the air-
craft thermocouple harness and aircraft ground.
The INSULATION CHECK meter is an ohmmeter
having two ranges-RX100 and RX1000. The circuit
is powered by a 9 vdc supply on the probe control
and function switch board.
(6) Resistance Check Circuit. T h e r e-
sistance check circuit is used to check and adjust
the resistance of the aircraft thermocouple circuit.
The RESISTANCE CHECK meter is the gal-
vanometer of a Wheatstone bridge. One leg of the
bridge contains a precision wirewound resistor se-
lected with the RESISTANCE & A/C INDICATOR
CHECK switch. The other leg contains the aircraft
thermocouple circuit (less the indicator). Correct re-
sistance is obtained in aircraft circuit by adjusting
resistance spool while observing galvanometers.
(7) Aircraft Indicator Check Circuit. T h is
circuit may be used to check the calibration of both
D-Arsonval and null-balance type egt indicators.
The appropriate aircraft indicator circuit is selected
with the RESISTANCE and A/C INDICATOR
CHECK switch. Calibration signals are adjusted
with the A/C IND ADJ while they are read on the
TEMP °C indicator. Calibration signals are com-
pared with aircraft indicator readings to determine
the error in the aircraft indicator.
b. Detailed Theory of Operation. The detailed
theory of operation will be discussed in the follow-
(1) A/d conversion.
(2) Temperature indicator.
Temperature signal circuits.
% rmp indicator.
% rpm signal circuits.
Standard day correction circuit.
Heater probe control circuit.
Insulation check circuit.
Resistance check circuit.
(10) Power supplies and power distribution.
(11) Logic circuitry.
Logic levels and integrated circuits used in the
tester are described in paragraph 1-4b, 1-11 c a nd
(1) A/D Conversion.
(a) An Overview. Figure 1-3 is a block dia-
gram of circuitry common to both tester A/D con-
verters. The A/D converters use the dual-slope in-
tegration technique. The slopes refer to the charge
and discharge curves of intergrating capacitor C,
figure 1-3. C is charged by the integrator during a
fixed interval of time called the signal integration
period when the amplified input signal is allowed to
pass through the signal field-effect transistor
(FET) switch and drive the integrator. The signal
integration period is controlled by the continuously
running clock oscillator, BCD decade counters,
BCD-DAC decoding, and FET switch control. At the
conclusion of the signal integration period, which is
the beginning of the reference integration period,
the counters are reset, the signal FET switch is
opened, and the appropriate reference FET switch
(+ or - reference) is closed. During the reference in-
tegration period, the integrating capacitor is dis-
charged by the integrator. The discharging voltage
is a +5 vdc if the input signal is negative and it is
the output of a precision negative reference voltage
divider if the input signal is positive. If the input
signal is in-range, the comparator detects the in-
stant the capacitor is completely discharged and
clocks flip-flop FF1A, causing the generation of a
transfer-to-memory pulse, ending the reference in-
tegration period. Transfer-to-memory (TRANSFER,
fig. 1-3) shifts the reference integration period
count, which represents the digitized input signal,
into the latches of the counter-latch-decoders, up-
dating the display. If the input signal is negative,
this fact is detected by FF2A at the start of the ref-
erence integration period and FF2A causes FF1A
to be cleared, generating transfer-to-memory. If the
input signal exceeds the range of the indicator, out-
of-range decoding causes FF1A to be cleared and
generate transfer-to-memory. A positive or nega-
1 - 4 A / ( 1 - 4 B b l a n k)